Two conventional approaches to implement photon sensors based on an array of single photon avalanche diodes (SPAD) operated in Geiger mode include analog silicon photo multipliers (SiPM), and digital silicon photomultipliers (dSiPM), also known as digital photon counters.
In conventional SiPM devices each individual SPAD is connected to a readout network via a quenching resistor having typical values between 100 KOhm-1 MOhm. A detected photon generates an avalanche, the SPAD capacitance discharges to a breakdown voltage and the recharging current creates a signal. Typical pulse shape of single photo electron (SPE) signal has a fast rise time, following a long fall time. As a result, pulse shape of a nuclear detector signal has a slow rise time (about a few tens of nanoseconds). These pulse shape characteristics make it difficult to achieve good time resolution.
Conventional dSiPM devices incorporate special electronic circuitry for each SPAD produced on the same silicon wafer. This circuitry is designed to detect avalanche and actively quench the SPAD. Each circuitry has a memory element (one to a few bits). A special network tree is used to collect time stamps from all the SPADs. A special read out cycle has to be executed to obtain information on the number of photons detected per event. This read out cycle requires a special digital controller for each dSiPM.
A SiPM pixel can include thousands of micro-cells. These micro-cells are conventionally arranged as an array. For analog SiPM pixels, the micro-cells in the pixel can be wire-summed together to output a signal in an analog fashion. Unlike the analog SiPM, a dSiPM pixel can include built-in electronics for each micro-cell.
FIG. 1 depicts a block diagram of conventional digital photon counter 100 that uses multiple dSiPM pixels 110. To read out timing, dSiPMs can include a complicated trigger network and an on-chip time-to-digital converter (TDC) fabricated on the same wafer. To read out energy, the dSiPM uses counter 130 connected to line 120 to scan the microcell array and count the number of firing microcells. The counter then outputs the final count accumulated during a predetermined time period to controller 150 as its digitized energy reading. The controller can be a field programmable gate array (FPGA). The counter and external controller can be connected by data bus 140.